|Speaker :||Davide Cuda|
|Time:||2:00 pm - 3:00 pm|
|Location:||LINCS Meeting Room 40|
Input-queued (IQ) switches are one of the referencearchitectures for the design of high-speed packet switches. Classical results in this field refer to the scenario in which the whole switch transfers the packets in a synchronous fashion, in phase with a sequence of fixed-size timeslots, selected to transport aminimum-size packet. However, for switches with large numberof ports and high bandwidth, maintaining an accurate global synchronization and transferring all the packets in a synchronousfashion is becoming more and more challenging. Furthermore,variable size packets (as in the traffic present in the Internet) require rather complex segmentation and reassembly processes and some switching capacity is lost due to partial filling of time slots. Thus, we consider a switch able to natively transfer packets in an asynchronous fashion thanks to a simple and distributed packet scheduler. We investigate the performance of synchronous IQ switches and show that, despite their simplicity, their performance is comparable or even better than those of synchronous switches. These partly unexpected results highlight the great potentiality of the asynchronous approach for the design of high-performance switches.