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BEGIN:VEVENT
UID:296@lincs.fr
DTSTART;TZID=Europe/Paris:20170405T140000
DTEND;TZID=Europe/Paris:20170405T150000
DTSTAMP:20170405T130414Z
URL:https://www.lincs.fr/events/stateful-programmable-data-planes/
SUMMARY:Stateful programmable data planes
DESCRIPTION:\n\n\nAbstract:\nIn Software Defined Networking (SDN) the
 control plane is physically separate from the forwarding plane. Control
 software programs the forwarding plane (e.g.\, switches and routers) using
 an open interface\, such as OpenFlow. SDN envisions smart centralized
 controllers governing the forwarding behaviour of dumb low-cost
 switches.Even if this approach presents several benefits (scalability\,
 vendor independence\, easiness of deployment etc.) it is often limited by
 the continuous intervention of the logically centralized controller (de
 facto complex distributed systems) to take decisions just based on local
 states (versus network-wide knowledge)\, which could be in principle
 directly handled at wire speed inside the device itself. Stateful dataplane
 processing is recently emerged as a enabling technology to supersede this
 limitation and to deploy virtual network functions at wire-speed.This talk
 will present Open Packet Processor (OPP)\, a stateful programmable
 dataplane abstraction that extend the OpenFlow match-action model adding
 the concept of a per-flow content that is used to represent the history of
 each flow travelling into the switch. OPP extracts a (configurable)
 flow-key from the incoming packet and update the flow content (and the
 associated forwarding decision) using some OpenFlow-like rules that define
 an Extended Finite State Machine (EFSM). The EFSM reads the current state\,
 the value of the flow-registers and the content of the packet and decide
 the next state\, update the flow-register values and set the action to
 apply to the packet.The talk will show an high-speed hardware
 implementation of a OPP based switch realized on an FPGA board with 4x10
 GbE ports and some use cases that leverage the features of the OPP
 abstraction. A comparison with the most relevant work in the field of
 stateful dataplane processing will be presented and compared with the OPP
 abstraction. Finally the talk will discuss the OPP limitations and
 extensions.\n\n\nBiography:\nSalvatore Pontarelli received the master
 Degree at university of Bologna in 2000. In 2003 takes its PhD degree in
 microelectronics and telecommunications from the University of Rome Tor
 Vergata. Currently\, he works as Researcher at CNIT (Italian Consortium of
 telecommunication)\, in the research unit of University of Rome Tor
 Vergata. In the past Dott. Pontarelli has worked with the National Research
 Council (CNR)\, the Department of Electronic Engineering of University of
 Rome Tor Vergata\, the Italian Space Agency (ASI)\, the University of
 Bristol.He also works as consultant for various Italian and International
 companies for design of hardware for high speed networking. He participates
 in several national and EU funded research program (ESA\, FP7 and H2020).
 In 2011 he was recipient of a CISCO research Award for the study on the
 combined use of Bloom filters and Ternary CAM. His main research activities
 are hash based structures for networking applications\, use of FPGA for
 high speed network monitoring\, hardware design of software defined network
 devices\, stateful programmable data planes.\n\n\n
CATEGORIES:Seminars,Youtube
LOCATION:LINCS Seminars room\, 23\, avenue d'Italie\, Paris\, 75013\,
 France
GEO:48.828400;2.356897
X-APPLE-STRUCTURED-LOCATION;VALUE=URI;X-ADDRESS=23\, avenue d'Italie\,
 Paris\, 75013\, France;X-APPLE-RADIUS=100;X-TITLE=LINCS Seminars
 room:geo:48.828400,2.356897
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TZID:Europe/Paris
X-LIC-LOCATION:Europe/Paris
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DTSTART:20170326T030000
TZOFFSETFROM:+0100
TZOFFSETTO:+0200
TZNAME:CEST
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